A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.

Researchers from the Massachusetts Institute of Technology have found a way to reduce data center energy usage. The team, from MIT's Computer Science and Artificial Intelligence laboratory (CSAIL), ...

A new paper from IIT Hyderabad in India surveys cache partitioning techniques for multicore processors. Now accepted in ACM Computing Surveys 2017, the survey by Sparsh Mittal reviews 90 papers. As ...

The year so far has been filled with news of Spectre and Meltdown. These exploits take advantage of features like speculative execution, and memory access timing. What they have in common is the fact ...

When shopping for a new CPU, you're likely to come across many different CPU specifications, such as cores, clock speed, TDP, ...

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...

In the eighties, computer processors became faster and faster, while memory access times stagnated and hindered additional performance increases. Something had to be done to speed up memory access and ...

Magneto-resistive random access memory (MRAM) is a non-volatile memory technology that relies on the (relative) magnetization state of two ferromagnetic layers to store binary information. Throughout ...

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver ...

A Cache-Only Memory Architecture design (COMA) may be a sort of Cache-Coherent Non-Uniform Memory Access (CC- NUMA) design. not like in a very typical CC-NUMA design, in a COMA, each shared-memory ...