SNPS expands its TSMC partnership, advancing AI, SoC, and multi-die design with certified flows, IP, and 3DIC innovations.

Synopsys and TSMC have partnered to accelerate the development of next-generation AI chips and multi-die designs.

AI and data center chips are hitting limits. A new 3D chip design improves speed, power use and memory bandwidth.

Launching a pilot 'chip design to tapeout' flow curriculum, enabling academic institutions with industry-aligned coursework. Pilot testing underway at over 40 select worldwide universities with intent ...

Learn real-world strategies about FPGA Chip Design, Join Elektor Engineering Insights on Sept 24 at 16:00 CEST with Kevin ...

Innovations in assistive AI and, ultimately, increased autonomy with agentic AI will redefine what engineers can achieve within the chip design cycle. Assistive AI: Improving chip design workflows.

Cadence (CDNS) announced major advancements in chip design automation and IP, driven by its long-standing relationship with TSMC (TSM) to develop ...

Siemens and TSMC deliver new certifications and design solutions for the foundry’s most advanced process technologies.

Programmable photonics devices, which use light to perform complex computations, are emerging as a key area in integrated ...

Microsoft says it may have found a better way to keep future AI chips cool, and it involves letting coolant flow right ...