Computers and water typically don't mix, but in Manu Prakash's lab, the two are one and the same. Prakash, an assistant professor of bioengineering at Stanford, and his students have built a ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

The synchronous vs. asynchronous design debate erupts every now and then, usually when a vocal minority swears by asynchronous design, often claiming that asynchronous design delivers higher ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

As the quest grows to manage power in everything from the handheld smart phone to sensors for automotive applications and contactless payment cards, designers are getting hungry for new design ...

Timing relationships between signals are critical to reliable operation of digital designs. With synchronous designs, the timing of the clock signal relative to data signals is especially important.

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...